In the previous article you learned to apply the Stuck at Fault Model (S@) to a small combinational circuit.

You can take the learning on the Full 1-bit adder and apply it to larger combinational circuit.

In testing lingo, you often hear people refer to this as the testing of random logic. Technically, there’s nothing random about the logic.

I think “random” gets used to contrast with the highly structured design of memory circuits into array of 1-bit cells. Memory test lends itself to algorithmic testing, for example the Marching 1. In random logic testing you may use algorithms to propagate your faults, that is automatically develop a test pattern.

You need to keep in mind that the logic being tested has a functional purpose and this can be implemented in a multitude of ways. Let’s take a second look at the adder function. [Read more…]

To work our ways towards understanding Design For Test (DFT)applications I am taking you back to the Stuck at Fault model (S@).

In the article which introduced you to the S@ model you learned the S@ model at the logic gate level.

Let’s build on this by applying it to combinational logic circuits.

Combinational logic has no clocked circuitry; sequential logic has clocked circuitry. In a few articles you’ll learn about test and sequential logic circuitry. [Read more…]

Semiconductor Integrated Circuits (ICs) can have millions of digital circuits which can translate to billions of transistors.

I know these numbers can be intimidating, but I assure you the challenges of testing ICs started in the mid-late 1970’s.  Lots of effort has been put into Electronic Design Automation (EDA) systems and Design for Test (DFT) techniques to manage the development and application of digital circuit testing.

In the beginning these software programs and DFT techniques used the Stuck at Fault Model. [Read more…]